Atomic-Scale Modeling of Nanoelectronic Devices

As device features near atomic dimensions, simulations of electrical currents need to be based on a quantummechanical description of the system rather than a classical one. New phenomena appear which can be exploited for novel device characteristics, but also fundamental challenges arise when the influence of single defects can have devastating effects. From a metrological perspective, the very definition of electrical current should be based on the quantum conductance, but in order to compare measurements and calculations accurately, a realistic atomistic description of the device configuration is required in order to properly describe impurities and defects. Although atomic-scale calculations of ballistic tunneling currents have become rather mainstream over the last decade, many challenges remain. Tight-binding models may work for some systems, but fail to capture the electronic structure of metallic systems, or interfaces combining metals and semiconducting materials, in which cases first-principles [1] or semi-empirical [2] approaches becomes necessary. For transistor applications it is necessary to include gates and dielectric screening regions, and in other cases we may need to consider sequential tunneling in the weak coupling limit [3], rather than the more common coherent tunneling picture. Moreover, all of the above needs to be carried out for large-scale systems that might involve thousands of atoms. We will provide an overview of these and other aspects of state-of-the-art atomic-scale modeling techniques, and show examples of how our software Atomistix ToolKit is used used to study a wide variety of nanoelectronic device structures, such as graphene field-effect transistors, conductance of nanowires, molecular junction diodes, contact resistance of metal-semiconductor interfaces, leakage currents in ultrathin oxide layers, and so on.